Existing buffers are challenging to design when competing performance parameters are desired to be maximized. For example, designing a buffer that can reject noise injected from a power supply rail connected to the buffer while providing high bandwidth for propagating an input signal from an input node of the buffer to its output node, while reducing inter-symbol interference (ISI), is challenging. Further, reducing power consumption of buffers is also needed because buffers are used in many places in a system-on-chip (SOC). Existing buffers when used in high bandwidth time interleaving analog-to-digital converters (TI ADCs), suffer from low power supply rejection ratio (PSRR), feedback induced memory effect (FME), and low ISI rejection.
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.